The present invention relates to hardware architectures for mathematical morphology operators, and more particularly, to hardware architectures for mathematical morphology operations such as image dilation or erosion, which can increase operation speed while decreasing the volume of hardware.
A mathematical morphology having a nonlinear characteristic is very effective in noise elimination, and pattern and edge preservation of signals. Thus, the mathematical morphology has been applied to an image signal processing field such as image dividing or defect detection. A linear system distorts the structure and morphology of the image when processing an image signal. Here, in order to solve this problem, a non-linear filter adopting the mathematical morphology has been mainly used. As elementary operators of the mathematical morphology, there are dilation and erosion. Also, there is a filter using opening, closing, opening-closing, and closing-opening operations by combining the dilation and erosion operators. Here, the opening and closing operations can be performed by repeating the erosion and dilation operations.
While the mathematical morphology having the excellent non-linear characteristic has been widely applied to an image signal processing area, a real-time processing cannot be performed using a software method due to an excessive amount of operations required therefor. Thus, research for solving the problem has been widely performed in aspects of hardware. Current structures of very large-scale integrated circuit (VLSI) related to the basic operation of the mathematical morphology are classified into two as follows.
First, there is a method for operating a gray-level image into a binary image, which is disclosed in an article entitled "Threshold Decomposition of Gray-Scale Morphology into Binary Morphology" written by F. Y. Shih and O. R. Miychell (IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. II, No. 1, January 1989). According to the article, a threshold decomposition is used for the image binarization, wherein a maximum value of a structuring element is fixed, thereby decreasing the volume of the hardware. However, the operation is impossible if the value of the structuring element is changed. Also, while the operation speed is fast since the operation is performed by a simple logic operation, the number of operations for the image binarization is increased.
Second, there is a method for performing an operation by finding maximum and minimum values of a gray-level image using an adder, which is disclosed in an article entitled "A Digital-serial Architecture for Gray-Scale morphological Filtering" written by L. Lucke and C. Chakrabarti (IEEE Trans. on Image processing, Vol. 4, No. 3, March 1995). According to the method, the volume of the hardware is small while the operation speed is slow. Also, there is a disadvantage of an increase in geometric progression of the hardware's volume according to the increase of the window's size of a structuring element.
FIG. 7 is a block diagram showing the structure of a conventional hardware architecture for dilation operation of an image signal, which is a 3.times.3 VSLI structure in which respective unit hardware is connected each other.
In unit hardware structures 71, 72 and 63, after adding a structuring element S.sub.mn to an original image I.sub.ij, the result is input to a comparator which compares the result with a result obtained by a neighboring pixel. As a result, a larger value between two compared results is selectively output. Also, the maximum value of the outputs from each unit hardware is selected by comparators 74 and 75 and the result is then output via an output register 76.
In the dilation operation, locations of the original image and the structuring element are symmetrical with respect to the origin. A total of four steps of comparison should be performed with respect to all 3.times.3 images. One adder is required for each pixel, and a total of eight comparators are required. The structuring element slides and operates with the original image during a window operation, so that there is no need for additionally storing an intermediate value of the operation. Thus, a total of nineteen registers are required, including nine for buffering an input image, nine for storing the values of structuring elements and one for synchronizing an output as an output buffer. The number of dilation operations is a total of five including one addition operation and four comparison operations.
FIG. 8 is a block diagram showing the structure of a conventional hardware architecture for erosion operation of an image signal, which is a 3.times.3 VLSI structure in which respective unit hardware is connected each other.
In unit hardware structures 81, 82 and 83, after subtracting a structuring element S.sub.mn from an original image I.sub.ij, the result is input to a comparator which compares the result with a result obtained by a neighboring pixel. As a result, a smaller value between two compared results is selectively output. Also, the minimum value of the outputs from each unit hardware is selected by comparators 84 and 85 and the result is then output via an output register 86.
The erosion operation is same as the dilation operation, except that the minimum value is found within the size of the structuring element after subtracting the value of the structuring element from that of the original image and the location of the structuring element is not symmetrical with respect to the origin. Comparing the basic structures of the unit hardware shown in FIGS. 7 and 8, the unit hardware of FIG. 8 includes a subtractor instead of an adder and the comparators of FIG. 8 select and output the minimum value between two values input to the comparators.
However, according to the conventional hardware architectures for the dilation and erosion operations, shown in FIGS. 7 and 8, the volume of the hardware is increased in geometric progression as the window's size of the structuring element increases.